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5.5 1 idt79r3081 riscontroller military and commercial temperature ranges military and commercial temperature ranges september 1995 1995 integrated device technology, inc. 5.5 dsc-9064/4 idt 79r3081 ? , 79r3081e idt 79rv3081, 79rv3081e idt79r3081 riscontroller ? with fpa r3081 block diagram clock generator unit/clock doubler master pipeline control system control coprocessor (cp0) integer cpu core exception/control registers memory management registers translation lookaside buffer (64 entries) general registers (32 x 32) alu shifter mult/div unit address adder pc control virtual address configurable data cache (4kb/8kb) configurable instruction cache (16kb/8kb) physical address bus biu control dma arbiter 4-deep write buffer clkin int(5:0) 32 36 brcond(3:2,0) data bus r3051 superset bus interface unit address/ data dma ctrl rd/wr ctrl sysclk register unit (16 x 64) exponent unit add unit divide unit multiply unit floating point coprocessor (cp1) coherency logic invalidate control exception/control data bus fp interrupt parity generator 4-deep read buffer 2889 drw 01 the idt logo is a registered trademark, and riscontroller, r3041, r3051, r3052, r3071, r3081, r3720, r4400, r4600, idt/kit, and idt/sim are trademarks of integrated device technology, inc. features ? instruction set compatible with idt79r3000a, r3041, r3051, and r3071 risc cpus ? high level of integration minimizes system cost r3000a compatible cpu r3010a compatible floating point accelerator optional r3000a compatible mmu large instruction cache large data cache read/write buffers ? 43vups at 50mhz 13mflops ? flexible bus interface allows simple, low cost designs ? optional 1x or 2x clock input ? 20 through 50mhz operation ? "v" version operates at 3.3v ? 50mhz at 1x clock input and 1/2 bus frequency only ? large on-chip caches with user configurability 16kb instruction cache, 4kb data cache dynamically configurable to 8kb instruction cache, 8kb data cache parity protection over data and tag fields ? low cost 84-pin packaging ? superset pin- and software-compatible with r3051, r3071 ? multiplexed bus interface with support for low-cost, low- speed memory systems with a high-speed cpu ? on-chip 4-deep write buffer eliminates memory write stalls ? on-chip 4-deep read buffer supports burst or simple block reads ? on-chip dma arbiter ? hardware-based cache coherency support ? programmable power reduction mode ? bus interface can operate at half-processor frequency integrated device technology, inc.
5.5 2 idt79r3081 riscontroller military and commercial temperature ranges the r3051, which incorporates 4kb of instruction cache and 2kb of data cache, but omits the tlb, and instead uses a simpler virtual to physical address mapping. the r3081e, which incorporates a 16kb instruction cache, a 4kb data cache, and full function memory management unit (mmu) including 64-entry fully associative translation lookaside buffer (tlb). the cache on the r3081e is user configurable to an 8kb instruction cache and 8kb data cache. the r3081, which incorporates a 16kb instruction cache, a 4kb data cache, but uses the simpler memory mapping of the r3051/52, and thus omits the tlb. the cache on the r3081 is user configurable to an 8kb instruction cache and 8kb data cache. figure 1 shows a block level representation of the functional units within the r3081e. the r3081e could be viewed as the embodiment of a discrete solution built around the r3000a and r3010a. however, by integrating this functionality on a single chip, dramatic cost and power reductions are achieved. cpu core the cpu core is a full 32-bit risc integer execution engine, capable of sustaining close to single cycle execution. the cpu core contains a five stage pipeline, and 32 orthogonal 32-bit registers. the r3081 uses the same basic integer execution core as the entire r3051 family, which is the r3000a implementation of the mips instruction set. thus, the r3081 family is binary compatible with the r3051, r3052, r3000a, r3001, and r3500 cpus. in addition, the r4000 represents an upwardly software compatible migration path to still higher levels of performance. the execution engine in the r3081 uses a five-stage pipeline to achieve near single-cycle instruction execution rates. a new instruction can be initiated in each clock cycle; the execution engine actually processes five instructions concurrently (in various pipeline stages). figure 2 shows the concurrency achieved in the r3081 execution pipeline. system control co-processor the r3081 family also integrates on-chip the system control co-processor, cp0. cp0 manages both the exception handling capability of the r3081, as well as the virtual to physical address mapping. as with the r3051 and r3052, the r3081 offers two versions of memory management and virtual to physical address mapping: the extended architecture versions, the r3051e, r3052e, and r3081e, incorporate the same mmu as the r3000a. these versions contain a fully associative 64- entry tlb which maps 4kb virtual pages into the physical address space. the virtual to physical mapping thus includes kernel segments which are hard-mapped to physical addresses, and kernel and user segments which are mapped page by page by the tlb into anywhere in the 4gb physical address space. in this tlb, 8 pages can be ?ocked?by the kernel to insure deterministic response in real-time applications. figure 3 illustrates the virtual to physical mapping found in the r3081e. introduction the idt r3051 family is a series of high-performance 32- bit microprocessors featuring a high-level of integration, and targeted to high-performance but cost sensitive processing applications. the r3051 family is designed to bring the high- performance inherent in the mips risc architecture into low-cost, simplified, power sensitive applications. thus, functional units have been integrated onto the cpu core in order to reduce the total system cost, rather than to increase the inherent performance of the integer engine. nevertheless, the r3051 family is able to offer 43vups performance at 50mhz without requiring external sram or caches. the r3081 extends the capabilities of the r3051 family, by integrating additional resources into the same pin-out. the r3081 thus extends the range of applications addressed by the r3051 family, and allows designers to implement a single, base system and software set capable of accepting a wide variety of cpus, according to the price/performance goals of the end system. in addition to the embedded applications served by the r3051 family, the r3081 allows low-cost, entry level computer systems to be constructed. these systems will offer many times the performance of traditional pc systems, yet cost approximately the same. the r3081 is able to run any standard r3000a operation system, including ace unix. thus, the r3081 can be used to build a low-cost arc compliant system, further widening the range of performance solutions of the ace initiative. an overview of this device, and quantitative electrical parameters and mechanical data, is found in this data sheet; consult the "r3081 family hardware user's guide" for a complete description of this processor. device overview as part of the r3051 family, the r3081 extends the offering of a wide range of functionality in a compatible interface. the r3051 family allows the system designer to implement a single base system, and utilize interface-compatible processors of various complexity to achieve the price-performance goals of the particular end system. differences among the various family members pertain to the on-chip resources of the processor. current family members include: the r3052e, which incorporates an 8kb instruction cache, a 2kb data cache, and full function memory management unit (mmu) including 64-entry fully associative translation lookaside buffer (tlb). the r3052, which also incorporates an 8kb instruction cache and 2kb data cache, but does not include the tlb, and instead uses a simpler virtual to physical address mapping. the r3051e, which incorporates 4kb of instruction cache and 2kb of data cache, along with the full function mmu/ tlb of the r3000a.
5.5 3 idt79r3081 riscontroller military and commercial temperature ranges the extended architecture versions of the r3051 family (the r3051e, r3052e, and r3081e) allow the system designer to implement kernel software which dynamically manages user task utilization of system resources, and also allows the kernel to protect certain resources from user tasks. these capabilities are important in general computing applications such as arc computers, and are also important in a variety of embedded applications, from process control (where protection may be important) to x-window display systems (where virtual memory management can be used). the mmu can also be used to simplify system debug. r3051 family base versions (the r3051, r3052, and r3081) remove the tlb and institute a fixed address mapping for the various segments of the virtual address space. these devices still support distinct kernel and user mode operation, but do not require page management software, leading to a simpler software model. the memory mapping used by these devices is shown in figure 4. note that the reserved spaces are for compatiblity with future family members, which may map on- chip resources to these addresses. references to these addresses in the r3081 will be translated in the same fashion as the rest of their respective segments, with no traps or exceptions signalled. when using the base versions of the architecture, the system designer can implement a distinction between the user tasks and the kernel tasks, without having to implement page management software. this distinction can be implemented by decoding the output physical address. in systems which do not need memory protection, and wish to have the kernel and user tasks operate out of the same memory space, high-order address lines can be ignored by the address decoder, and thus all references will be seen in the lower gigabyte of the physical address space. floating point co-processor the r3081 also integrates an r3010a compatible floating point accelerator on-chip. the fpa is a high-performance co- processor (co-processor 1 to the cpu) providing separate add, multiply, and divide functional units for single and double precision floating point arithmetic. the floating point accelerator features low latency operations, and autonomous functional units which allow differing types of floating point operations to function concurrently with integer operations. the r3010a appears to the software programmer as a simple extension of the integer execution unit, with 16 dedicated 64-bit floating point registers (software references these as 32 32-bit registers when performing loads or stores). figure 5 illustrates the functional block diagram of the on-chip fpa. clock generator unit the r3081 is driven from a single input clock which can be either at the processor rated speed, or at twice that speed. on- chip, the clock generator unit is responsible for managing the interaction of the cpu core, caches, and bus interface. the r3081 includes an on-chip clock doubler to provide higher frequency signals to the internal execution core; if 1x clock mode is selected, the clock doubler will internally convert it to figure 4. virtual to physical mapping of base architecture versions 1mb kernel rsvd kernel cacheable tasks kernel/user cacheable tasks inaccessible kernel boot and i/o 0xffffffff 0xc0000000 0xa0000000 0x80000000 0x00000000 1024 mb 2048 mb 512 mb 512 mb virtual physical kernel cached (kseg2) kernel uncached (kseg1) kernel cached (kseg0) user cached (kuseg) 1mb user rsvd 2889 drw 04 figure 3. virtual to physical mapping of extended architecture versions kernel mapped (kseg2) kernel uncached (kseg1) kernel cached (kseg0) user mapped cacheable (kuseg) physical memory memory 0xffffffff 0xc0000000 0xa0000000 0x80000000 0x00000000 3548mb 512 mb any any virtual physical 2889 drw 03 figure 2. r3081 5-stage pipeline if current cpu cycle i#1 alu rd mem wb if i#2 alu rd mem wb if i#3 alu rd mem wb if i#4 alu rd mem wb if i#5 alu rd mem wb 2889 drw 02
5.5 4 idt79r3081 riscontroller military and commercial temperature ranges a double frequency clock. the 2x clock mode is provided for compatiblity with the r3051. the clock generator unit replaces the external delay line required in r3000a based applications. instruction cache the r3081 implements a 16kb instruction cache. the system may choose to repartition the on-chip caches, so that the instruction cache is reduced to 8kb but the data cache is increased to 8kb. the instruction cache is organized with a line size of 16bytes (four entries). this large cache achieves hit rates in excess of 98% in most applications, and substantially contributes to the performance inherent in the r3081. the cache is implemented as a direct mapped cache, and is capable of caching instructions from anywhere within the 4gb physical address space. the cache is implemented using physical addresses (rather than virtual addresses), and thus does not require flushing on context switch. the instruction cache is parity protected over the instruction word and tag fields. parity is generated by the read buffer during cache refill; during cache references, the parity is checked, and in the case of a parity error, a cache miss is processed. data cache the r3081 incorporates an on-chip data cache of 4kb, organized as a line size of 4 bytes (one word). the r3081 allows the system to reconfigure the on-chip cache from the default 16kb i-cache/4kb d-cache to 8kb of instruction and 8kb of data caches. the relatively large data cache achieves hit rates in excess of 95% in most applications, and contributes substantially to the performance inherent in the r3081. as with the instruction cache, the data cache is implemented as a direct mapped physical address cache. the cache is capable of mapping any word within the 4gb physical address space. the data cache is implemented as a write-through cache, to insure that main memory is always consistent with the internal cache. in order to minimize processor stalls due to data write operations, the bus interface unit incorporates a 4- deep write buffer which captures address and data at the processor execution rate, allowing it to be retired to main memory at a much slower rate without impacting system performance. further, support has been provided to allow hardware based data cache coherency in a multi-master environment, such as one utilizing dma from i/o to memory. the data cache is parity protected over the data and tag fields. parity is generated by the read buffer during cache refill; during cache references, the parity is checked, and in the case of a parity error, a cache miss is processed. bus interface unit the r3081 uses its large internal caches to provide the majority of the bandwidth requirements of the execution engine, and thus can utilize a simple bus interface connected to slower memory devices. alternately, a high-performance, low-cost secondary cache can be implemented, allowing the processor to increase performance in systems where bus bandwidth is a performance limitation. as part of the r3051 family, the r3081 bus interface utilizes a 32-bit address and data bus multiplexed onto a single set of pins. the bus interface unit also provides an ale (address latch enable) output signal to de-multiplex the a/d bus, and figure 5. fpa functional block diagram cache data data bus instructions operands condition codes exponent part fraction register unit (16 x 64) (32) (32) control unit and clocks (11) (11) (11) (53) (53) (53) (53) (53) (56) (53) (53) (56) a b result result exponent unit ab add unit round result ab result ab divide unit multiply unit 2889 drw 05
5.5 5 idt79r3081 riscontroller military and commercial temperature ranges simple handshake signals to process cpu read and write requests. in addition to the read and write interface, the r3051 family incorporates a dma arbiter, to allow an external master to control the external bus. the r3081 also supports hardware based cache coherency during dma writes. the r3081 can invalidate a specified line of data cache, or in fact can perform burst invalidations during burst dma writes. the r3081 incorporates a 4-deep write buffer to decouple the speed of the execution engine from the speed of the memory system. the write buffers capture and fifo processor address and data information in store operations, and present it to the bus interface as write transactions at the rate the memory system can accommodate. the r3081 read interface performs both single datum reads and quad word reads. single reads work with a simple handshake, and quad word reads can either utilize the simple handshake (in lower performance, simple systems) or utilize a tighter timing mode when the memory system can burst data at the processor clock rate. thus, the system designer can choose to utilize page or nibble mode drams (and possibly use interleaving, if desired, in high-performance systems), or use simpler techniques to reduce complexity. in order to accommodate slower quad word reads, the r3081 incorporates a 4-deep read buffer fifo, so that the external interface can queue up data within the processor before releasing it to perform a burst fill of the internal caches. the r3081 is r3051 superset compatible in its bus interface. specifically, the r3081 has additional support to simplify the design of very high frequency systems. this support includes the ability to run the bus interface at one-half the processor execution rate, as well as the ability to slow the transitions between reads and writes to provide extra buffer disable time for the memory interface. however, it is still possible to design a system which, with no modification to the pc board or software, can accept either an r3041, r3051, r3052, r3071, or r3081. system usage the idt r3051 family has been specifically designed to allow a wide variety of memory systems. low-cost systems can use slow speed memories and simple controllers, while other designers may choose to incorporate higher frequencies, faster memories, and techniques such as dma to achieve maximum performance. the r3081 includes specific support for high perfromance systems, including signals necessary to implement external secondary caches, and the ability to perform hardware based cache coherency in multi-master systems. figure 6 shows a typical system implementation. transparent latches are used to de-multiplex the r3081 address and data busses from the a/d bus. the data paths between the memory system elements and the a/d bus is managed by simple octal devices. a small set of simple pals is used to control the various data path elements, and to control the handshake between the memory devices and the cpu. depending on the cost vs. performance tradeoffs appropriate to a given application, the system design engineer could include true burst support from the dram to provide for high- performance cache miss processing, or utilize a simpler, lower performance memory system to reduce cost and simplify the design. similarly, the system designer could choose to implement techniques such as external secondary cache, or dma, to further improve system performance. development support the idt r3051 family is supported by a rich set of development tools, ranging from system simulation tools through prom monitor and debug support, applications software and utility libraries, logic analysis tools, sub-system modules, and shrink wrap operating systems. the r3081, which is pin and software compatible with the r3051, can directly utilize these existing tools to reduce time to market. figure 7 is an overview of the system development process typically used when developing r3051 family applications. the r3051 family is supported in all phases of project development. these tools allow timely, parallel development of hardware and software for r3051 family applications, and include tools such as: optimizing compilers from mips, the acknowledged leader in optimizing compiler technology. cross development tools, available in a variety of development environments. the idt evaluation board, which includes ram, eprom, i/o, and the idt prom monitor. idt/sim ? , which implements a full prom monitor (diagnostics, remote debug support, peek/poke, etc.). idt/kit ? , which implements a run-time support package for r3051 family systems. performance overview the r3081 achieves a very high-level of performance. this performance is based on: an efficient execution engine. the cpu performs alu operations and store operations in a single cycle, and has an effective load time of 1.3 cycles, and branch execution rate of 1.5 cycles (based on the ability of the compilers to avoid software interlocks). thus, the execution engine achieves over 35 vups performance when operating out of cache. a full featured floating point accelerator/co-processor. the r3081 incorporates an r3010a compatible floating point accelerator on-chip, with independent alus for floating point add, multiply, and divide. the floating point unit is fully hardware interlocked, and features overlapped operation and precise exceptions. the fpa allows floating point adds, multiplies, and divides to occur concurrently with each other, as well as concurrently with integer operations. large on-chip caches. the r3051 family contains caches which are substantially larger than those on the majority of today? microprocessors. these large caches minimize the number of bus transactions required, and allow the r3051 family to achieve actual sustained performance very close to its peak execution rate. the r3081 doubles the cache available on the r3052, making it a suitable engine for
5.5 6 idt79r3081 riscontroller military and commercial temperature ranges figure 6. r3081 rischipset based system clkin idt r3081 riscontroller address/data control i/o controller dram controller dram dram prom i/o i/o idt73720 bus exchanger r3051 local bus 2889 drw 06 figure 7. r3051 family development toolchain cache-3051 spp benchmarks evaluation board laser printer system x-terminal system dbg debugger pixie profiler mips compiler suite stand-alone libraries floating point library cross development tools adobe postscript pdl microsoft trueimage pdl peerlesspage printer os x-server hardware models general cad tools evaluation board laser printer system support chips logic analysis diagnostics idt/sim idt/kit in-circuit emulation remote debug real-time os software hardware system integration and verfification system development phase system architecture evaluation 2889 drw 07
5.5 7 idt79r3081 riscontroller military and commercial temperature ranges many general purpose computing applications, such as arc compliant systems. autonomous multiply and divide operations. the r3051 family features an on-chip integer multiplier/divide unit which is separate from the other alu. this allows the cpu to perform multiply or divide operations in parallel with other integer operations, using a single multiply or divide instruction rather than ?tep?operations. integrated write buffer. the r3081 features a four deep write buffer, which captures store target addresses and data at the processor execution rate and retires it to main memory at the slower main memory access rate. use of on- chip write buffers eliminates the need for the processor to stall when performing store operations. burst read support. the r3051 family enables the system designer to utilize page mode or nibble mode rams when performing read operations to minimize the main memory read penalty and increase the effective cache hit rates. these techniques combine to allow the processor to achieve over 43 vups integer performance, 13mflops of linpack performance, and 70,000 dhrystones without the use of external caches or zero wait-state memory devices. the performance differences between the various family members depends on the application software and the design of the memory system. the impact of the various cache sizes, and the hardware floating point, can be accurately modeled using cache-3051. since the r3041, r3051, r3052, r3071, and r3081 are all pin and software compatible, the system designer has maximum freedom in trading between performance and cost. a system can be designed, and later the appropriate cpu inserted into the board, depending on the desired system performance. selectable features the r3081 allows the system designer to configure certain aspects of operation. some of these options are established when the device is reset, while others are enabled via the config registers: bigendian vs. littleendian byte ordering. the part can be configured to operate with either byte ordering. ace/ arc systems typically use little endian byte ordering. however, various embedded applications, written originally for a big endian processor such as the mc680x0, are easier to port to a big endian system. data cache refill of one or four words. the memory system must be capable of performing four word refills of instruction cache misses. the r3081 allows the system designer to enable d-cache refill of one or four words dynamically. thus, specialized algorithms can choose one refill size, while the rest of the system can operate with the other. half-frequency bus mode. the processor can be configured such that the external bus interface is at one- half the frequency of the processor core. this simplifies system design; however, the large on-chip caches mitigate the performance impact of using a slower system bus clock. slow bus turn-around. the r3081 allows the system designer to space processor operations, so that more time is allowed for transitions between memory and the processor on the multiplexed address/data bus. configurable cache. the r3081 allows the system designer to use software to select either a 16kb instruction cache/4kb data cache organization, or an 8kb instruction/ 8kb data cache organization. cache coherent interface. the r3081 has an optional hardware based cache coherency interface intended to support multi-master systems such as those utilizing dma between memory and i/o. optional 1x or 2x clock input. the r3081 can be driven with an r3051 compatible 2x clock input, or a lower frequency 1x clock input. thermal considerations the r3081 utilizes special packaging techniques to improve the thermal properties of high-speed processors. thus, the r3081 is packaged using cavity down packaging, with an embedded thermal slug to improve thermal transfer to the suurrounding air. the r3081 utilizes the 84-pin mquad package (the "mj" package), which is an all aluminum package with the die attached to a normal copper lead-frame mounted to the aluminum casing. the mquad package allows for an efficient thermal transfer between the die and the case due to the heat spreading effect of the aluminum. the aluminum offers less internal resistance from one end of the package to the other, reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the pcb for a given temperature. even nominal amounts of airflow will dramatically reduce the junction temperature of the die, resulting in cooler operation. the mquad package is available at all frequencies, and is pin and form compatible with the plcc used for the r3051. thus, designers can inter-change r3081s and r3051s in a particular design, without changing their pc board. the r3081 is guaranteed in a case temperature range of 0 c to +85 c. the type of package, speed (power) of the device, and airflow conditions, affect the equivalent ambient temperature conditions which will meet this specification. the equivalent allowable ambient temperature, t a , can be calculated using the thermal resistance from case to ambient ( ca ) of the given package. the following equation relates ambient and case temperatures: t a = t c - p * ca where p is the maximum power consumption at hot temperature, calculated by using the maximum icc specification for the device. typical values for ca at various airflows are shown in table 1. note that the r3081 allows the operational frequency to be turned down during idle periods to reduce power consumption. this operation is described in the r3081 hardware user's guide . reducing the operation frequency dramatically reduces power consumption.
5.5 8 idt79r3081 riscontroller military and commercial temperature ranges ca airflow (ft/min) 0 200 400 600 800 1000 "mj" package* 22 14 12 11 9 8 plcc package 29 26 21 18 16 15 2889 tbl 01 table 1. thermal resistance ( ca ) at various airflows (*estimated: final values tbd) notes on system design the r3081 has been designed to simplify the task of high- speed system design. thus, set-up and hold-time requirements have been kept to a minimum, allowing a wide variety of system interface strategies. to minimize these ac parameters, the r3081 employs feedback from its sysclk output to the internal bus interface unit. this allows the r3081 to reference input signals to the reference clock seen by the external system. the sysclk output is designed to provide relatively large ac drive to minimize skew due to slow rise or fall times. a typical part will have less than 2ns rise or fall (10% to 90% signal times) when driving the test load. therefore, the system designer should use care when designing for direct sysclk use. total loading (due to devices connected on the signal net and the routing of the net itself) should be minimized to ensure the sysclk output has a smooth and rapid transition. long rise and/or fall times may cause a degradation in the speed capability of an individual device. similarly, the r3081 employs feedback on its ale output to ensure adequate address hold time to ale. the system designer should be careful when designing the ale net to minimize total loading and to minimize skew between ale and the a/d bus, which will ensure adequate address access latch time. idt's field and factory applications groups can provide the system designer with assistance for these and other design issues.
5.5 9 idt79r3081 riscontroller military and commercial temperature ranges pin description pin name i/o description a/d(31:0) i/o address/data: a 32-bit time multiplexed bus which indicates the desired address for a bus transaction in one phase, and which is used to transmit data between the cpu and external memory resources during the rest of the transfer. bus transactions on this bus are logically separated into two phases: during the first phase, information about the transfer is presented to the memory system to be captured using the ale output. this information consists of: address(31:4) : the high-order address for the transfer is presented on a/d(31:4). be be (3:0) : these strobes indicate which bytes of the 32-bit bus will be involved in the transfer, and are presented on a/d(3:0). during write cycles, the bus contains the data to be stored and is driven from the internal write buffer. on read cycles, the bus receives the data from the external resource, in either a single data transaction or in a burst of four words, and places it into the on-chip read buffer. during cache coherency operations, the r3081 monitors the a/d bus at the start of a dma write to capture the write target address for potential data cache invalidates. addr(3:2) o low address (3:2) a 2-bit bus which indicates which word is currently expected by the processor. specifically, this two bit bus presents either the address bits for the single word to be transferred (writes or single datum reads) or functions as a two bit counter starting at 00 for burst read operations. during cache coherency operations, the r3081 monitors the addr bus at the start of a dma write to capture the write target address for potential data cache invalidates. diag(1) o diagnostic pin 1. this output indicates whether the current bus read transaction is due to an on-chip cache miss, and also presents part of the miss address. the value output on this pin is time multiplexed: cached: during the phase in which the a/d bus presents address information, this pin is an active high output which indicates whether the current read is a result of a cache miss. miss address (3): during the remainder of the read operation, this output presents address bit (3) of the address the processor was attempting to reference when the cache miss occurred. regardless of whether a cache miss is being processed, this pin reports the transfer address during this time. on write cycles, this output signals whether the data being written as retained in the on-chip data cache. the value of this pin is time multiplexed during writes: cached: during the address phase of write transactions, this signal is an active high output which indicates that the store data was retained in the on-chip data cache. reserved: the value of this pin during the data phase of writes is reserved. diag(0) o diagnostic pin 0. this output distinguishes cache misses due to instruction references from those due to data references, and presents the remaining bit of the miss address. the value output on this pin is also time multiplexed: i/ d d : if the cached pin indicates a cache miss, then a high on this pin at this time indicates an instruction reference, and a low indicates a data reference. if the read is not due to a cache miss but rather an uncached reference, then this pin is undefined during this phase. miss address (2): during the remainder of the read operation, this output presents address bit (2) of the address the processor was attempting to reference when the cache miss occurred. regardless of whether a cache miss is being processed, this pin reports the transfer address during this time. during write cycles, the value of this pin during both the address and data phases is reserved. 2889 tbl 02
5.5 10 idt79r3081 riscontroller military and commercial temperature ranges pin description (continued): pin name i/o description ale i/o address latch enable: used to indicate that the a/d bus contains valid address information for the bus transaction. this signal is used by external logic to capture the address for the transfer, typically using transparent latches. during cache coherency operations, the r3081 monitors ale at the start of a dma write, to capture the write target address for potential data cache invalidates. rd o read: an output which indicates that the current bus transaction is a read. wr i/o write: an output which indicates that the current bus transaction is a write. during coherent dma, this input indicates that the current transfer is a write. dataen o external data enable: this signal indicates that the a/d bus is no longer being driven by the processor during read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus without having a bus conflict occur. during write cycles, or when no bus transaction is occurring, this signal is negated, thus disabling the external memory drivers burst/ o burst transfer/write near: on read transactions, the burst signal indicates that the current bus read is wrnear requesting a block of four contiguous words from memory. this signal is asserted only in read cycles due to cache misses; it is asserted for all i-cache miss read cycles, and for d-cache miss read cycles if quad word refill is currently selected. on write transactions, the wrnear output tells the external memory system that the bus interface unit is performing back-to-back write transactions to an address within the same 512 word page as the prior write transaction. this signal is useful in memory systems which employ page mode or static column drams, and allows near writes to be retired quickly. ack i acknowledge: an input which indicates to the device that the memory system has sufficiently processed the bus transaction, and that the cpu may either terminate the write cycle or process the read data from this read transfer. during coherent dma, this input indicates that the current write transfer is completed, and that the internal invalidation address counter should be incremented. rdcen i read buffer clock enable: an input which indicates to the device that the memory system has placed valid data on the a/d bus, and that the processor may move the data into the on-chip read buffer. sysclk o system reference clock: an output from the cpu which reflects the timing of the internal processor "sys" clock. this clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus interface unit. this clock will either be at the same frequency as the cpu execution rate clock, or at one-half that frequency, as selected during reset. busreq i dma arbiter bus request: an input to the device which requests that the cpu tri-state its bus interface signals so that they may be driven by an external master. busgnt o dma arbiter bus grant. an output from the cpu used to acknowledge that a busreq has been detected, and that the bus is relinquished to the external master. ivdreq i invalidate request. an input provided by an external dma controller to request that the cpu invalidate the data cache line corresponding to the current dma write target address. this signal is the same pin as diag(0) cohreq i coherent dma request. an input used by the external dma controller to indicate that the requested dma operations could involve hardware cache coherency. this signal is the rsvd(0) of the r3051. sbrcond(3:2) i branch condition port: these external signals are internally connected to the cpu signals cpcond(3:0). brcond(0) these signals can be used by the branch on co-processor condition instructions as input ports. there are two types of branch condition inputs: the sbrcond inputs have special internal logic to synchronize the inputs, and thus may be driven by asynchronous agents. the direct branch condition inputs must be driven synchronously. note that brcond(1) is used by the internal fpa, and thus is not available on an external pin. buserror i bus error: input to the bus interface unit to terminate a bus transaction due to an external bus error. this signal is only sampled during read and write operations. if the bus transaction is a read operation, then the cpu will take a bus error exception. 2889 tbl 03
5.5 11 idt79r3081 riscontroller military and commercial temperature ranges pin name i/o description int (5:3) i processor interrupt: during normal operation, these signals are logically the same as the int (5:0) sint (2:0) signals of the r3000. during processor reset, these signals perform mode initialization of the cpu, but in a different (simpler) fashion than the interrupt signals of the r3000. there are two types of interrupt inputs: the sint inputs are internally synchronized by the processor, and may be driven by an asynchronous external agent. the direct interrupt inputs are not internally synchronized, and thus must be externally synchronized to the cpu. the direct interrupt inputs have one cycle lower latency than the synchronized interrupts. note that the interrupt used by the on-chip fpa will not be monitored externally. clkin i master clock input: this input clock can be provided at the execution frequency of the cpu (1x clock mode) or at twice that frequency (2x clock mode), as selected at reset. reset i master processor reset: this signal initializes the cpu. mode selection is performed during the last cycle of reset . rsvd(4:1) i/o reserved: these four signal pins are reserved for testing and for future revisions of this device. users must not connect these pins. note that rsvd(0) of the r3051 is now used for the cohreq input pin. pin description (continued): absolute maximum ratings (1, 3) symbol rating commercial military unit v term terminal voltage C0.5 to +7.0 C0.5 to +7.0 v with respect to gnd t c operating case 0 to +85 C55 to +125 c temperature t bias case temperature C55 to +125 C65 to +135 c under bias t stg storage C55 to +125 C65 to +155 c temperature v in input voltage C0.5 to +7.0 C0.5 to +7.0 v notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = C3.0v for pulse width less than 15ns. v in should not exceed v cc +0.5v. 3. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. 2889 tbl 05 output loading for ac testing signal c ld sysclk 50 pf all others 25 pf 2889 tbl 08 symbol parameter min. max. unit v ih input high voltage 3.0 v v il input low voltage 0 v v ihs input high voltage 3.0 v v ils input low voltage 0 v 2889 tbl 06 ac test conditions?v3081 C + to device under test c ld C4ma +4ma v ref +1.5v 2889 drw 08 ac test conditions?3081 2889 tbl 06 symbol parameter min. max. unit v ih input high voltage 3.0 v v il input low voltage 0 v v ihs input high voltage 3.5 v v ils input low voltage 0 v 2889 tbl 04 recommended operating temperature and supply voltage 2889 tbl 07 grade temperature(case) gnd v cc military C55 c to +125 c 0v 5.0 10% commercial 0 c to +85 c 0v 5.0 5% commercial 0 c to +85 c 0v 3.3 5%
5.5 12 idt79r3081 riscontroller military and commercial temperature ranges 20mhz 25mhz symbol parameter test conditions min. max. min. max. units v oh output high voltage v cc = min., i oh = C4ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4ma 0.4 0.4 v v ih input high voltage (3) 2.0 2.0 v v il input low voltage (1) 0.8 0.8 v v ihs input high voltage (2,3) 2.8 2.8 v v ils input low voltage (1,2) 0.4 0.4 v c in input capacitance (4,5) 10 10 pf c out output capacitance (4,5) 10 10 pf i cc operating current v cc = 3.3v, t a = 25 c 375 425 ma i ih input high leakage v ih = vcc 100 100 m a i il input low leakage v il = gnd C100 C100 m a i oz output tri-state leakage v oh = 2.4v, v ol = 0.5v C100 100 C100 100 m a dc electrical characteristics rv3081 commercial temperature range (1, 2) ? (t c = 0 c to +85 c, v cc = +3.3v 5%) 2889 tbl 09 notes: 1. v il min. = C3.0v for pulse width less than 15ns. v il should not fall below -0.5v for larger periods. 2. v ihs and v ils apply to cikin and reset . 3. v ih should not be held above v cc + 0.5v. 4. guaranteed by design. 5. ale is 12pf for sysclk values c in and c out for all speeds. ac electrical characteristics rv3081 commercial temperature range (1, 2) ? (t c = 0 c to +85 c, v cc = +3.3v 5%) 20mhz 25mhz symbol signals description min. max. min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 6 5 ns rdcen , cohreq t1a a/d set-up to sysclk falling 7 6 ns t2 busreq , ack , buserror , hold from sysclk rising 4 4 ns rdcen , cohreq t2a a/d hold from sysclk falling 2 2 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 10 10 ns burst / wrnear , rd , dataen t4 a/d, addr, diag, ale, wr driven from sysclk falling 10 10 ns burst / wrnear , rd , dataen t5 busgnt asserted from sysclk rising 8 7 ns t6 busgnt negated from sysclk falling 8 7 ns t7 wr , rd , burst / wrnear , a/d valid from sysclk rising 5 5 ns t8 ale asserted from sysclk rising 4 4 ns t9 ale negated from sysclk falling 4 4 ns t10 a/d hold from ale negated (3) 2 2 ns t11 dataen asserted from sysclk falling 15 15 ns t12 dataen asserted from a/d tri-state (3) 0 0 ns t14 a/d driven from sysclk rising (3) 0 0 ns t15 wr , rd , dataen , burst / wrnear negated from sysclk falling 7 6 ns t16 addr(3:2) valid from sysclk 6 6 ns t17 diag valid from sysclk 12 11 ns
5.5 13 idt79r3081 riscontroller military and commercial temperature ranges ac electrical characteristics rv3081 (cont.) commercial temperature range (1, 2) ? (t c = 0 c to +85 c, v cc = +3.3v 5%) 20mhz 25mhz symbol signals description min. max. min. max. unit t18 a/d tri-state from sysclk falling 10 10 ns t19 a/d sysclk falling to data valid 13 12 ns t20 clkin (2x clock mode) pulse width high 10 8 ns t21 clkin (2x clock mode) pulse width low 10 8 ns t22 clkin (2x clock mode) clock period 25 250 20 250 ns t23 reset pulse width from vcc valid 200 200 m s t24 reset minimum pulse width 32 32 tsys t25 reset set-up to sysclk falling 6 5 ns t26 int mode set-up to reset rising 10 9 ns t27 int mode hold from reset rising 0 0 ns t28 sint , sbrcond set-up to sysclk falling 6 5 ns t29 sint , sbrcond hold from sysclk falling 3 3 ns t30 int , brcond set-up to sysclk falling 6 5 ns t31 int , brcond hold from sysclk falling 3 3 ns tsys sysclk (full frequency mode) pulse width (5) 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk (full frequency mode) clock high time (5) t22-2 t22+2 t22-2 t22+2 ns t33 sysclk (full frequency mode) clock low time (5) t22-2 t22+2 t22-2 t22+2 ns tsys/2 sysclk (half frequency mode) pulse width (5) 4*t22 4*t22 4*t22 4*t22 4*t22 ns t34 sysclk (half frequency mode) clock high time (5) 2*t22-2 2*t22+2 2*t22-2 2*t22+2 ns t35 sysclk (half frequency mode) clock low time (5) 2*t22-2 2*t22+2 2*t22-2 2*t22+2 ns t36 aleset-up to sysclk falling 9 8 ns t37 alehold from sysclk falling 2 2 ns t38 a/dset-up to ale falling 10 9 ns t39 a/dhold from ale falling 2 2 ns t40 wr set-up to sysclk rising 10 9 ns t41 wr hold from sysclk rising 3 3 ns t42 clkin (1x clock mode) pulse width high (6) 20 16 ns t43 clkin (1x clock mode) pulse width low (6) 20 16 ns t44 clkin (1x clock mode) clock period (6) 50 50 40 50 ns tderate all outputs timing deration for loading 1 1 ns/ over c ld (3, 4) 25pf notes: 2889 tbl 11 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns.
5.5 14 idt79r3081 riscontroller military and commercial temperature ranges 33mhz 40mhz symbol parameter test conditions min. max. min. max. units v oh output high voltage v cc = min., i oh = C4ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4ma 0.4 0.4 v v ih input high voltage (3) 2.0 2.0 v v il input low voltage (1) 0.8 0.8 v v ihs input high voltage (2,3) 2.8 2.8 v v ils input low voltage (1,2) 0.4 0.4 v c in input capacitance (4,5) 10 10 pf c out output capacitance (4,5) 10 10 pf i cc operating current v cc = 3.3v, t a = 25 c 525 600 ma i ih input high leakage v ih = vcc 100 100 m a i il input low leakage v il = gnd C100 C100 m a i oz output tri-state leakage v oh = 2.4v, v ol = 0.5v C100 100 C100 100 m a dc electrical characteristics rv3081 commercial temperature range (1, 2) ? (t c = 0 c to +85 c, v cc = +3.3v 5%) 2889 tbl 09 notes: 1. v il min. = C3.0v for pulse width less than 15ns. v il should not fall below -0.5v for larger periods. 2. v ihs and v ils apply to cikin and reset . 3. v ih should not be held above v cc + 0.5v. 4. guaranteed by design. 5. ale is 12pf for sysclk values c in and c out for all speeds. ac electrical characteristics rv3081 commercial temperature range (1, 2) ? (t c = 0 c to +85 c, v cc = +3.3v 5%) 33mhz 40mhz symbol signals description min. max. min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 4 3 ns rdcen , cohreq3 t1a a/d set-up to sysclk falling 5 4.5 ns t2 busreq , ack , buserror , hold from sysclk rising 3 3 ns rdcen , cohreq t2a a/d hold from sysclk falling 1 1 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 10 10 ns burst / wrnear , rd , dataen t4 a/d, addr, diag, ale, wr driven from sysclk falling 10 10 ns burst / wrnear , rd , dataen t5 busgnt asserted from sysclk rising 6 5 ns t6 busgnt negated from sysclk falling 6 5 ns t7 wr , rd , burst / wrnear , a/d valid from sysclk rising 4 3.5 ns t8 ale asserted from sysclk rising 3 3 ns t9 ale negated from sysclk falling 3 3 ns t10 a/d hold from ale negated (3) 1.5 1.5 ns t11 dataen asserted from sysclk falling 13 12 ns t12 dataen asserted from a/d tri-state (3) 0 0 ns t14 a/d driven from sysclk rising (3) 0 0 ns t15 wr , rd , dataen , burst / wrnear negated from sysclk falling 5 4 ns t16 addr(3:2) valid from sysclk 5 4.5 ns t17 diag valid from sysclk 10 9 ns
5.5 15 idt79r3081 riscontroller military and commercial temperature ranges ac electrical characteristics rv3081 (cont.) commercial temperature range (1, 2) ? (t c = 0 c to +85 c, v cc = +3.3v 5%) 33mhz 40mhz symbol signals description min. max. min. max. unit t18 a/d tri-state from sysclk falling 9 8 ns t19 a/d sysclk falling to data valid 11 10 ns t20 clkin (2x clock mode) pulse width high 6.5 5.6 ns t21 clkin (2x clock mode) pulse width low 6.5 5.6 ns t22 clkin (2x clock mode) clock period 15 250 12.5 250 ns t23 reset pulse width from vcc valid 200 200 m s t24 reset minimum pulse width 32 32 tsys t25 reset set-up to sysclk falling 4 3 ns t26 int mode set-up to reset rising 8 7 ns t27 int mode hold from reset rising 0 0 ns t28 sint , sbrcond set-up to sysclk falling 4 3 ns t29 sint , sbrcond hold from sysclk falling 2 2 ns t30 int , brcond set-up to sysclk falling 4 3 ns t31 int , brcond hold from sysclk falling 2 2 ns tsys sysclk (full frequency mode) pulse width (5) 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk (full frequency mode) clock high time (5) t22-1 t22+1 t22-1 t22+1 ns t33 sysclk (full frequency mode) clock low time (5) t22-1 t22+1 t22-1 t22+1 ns tsys/2 sysclk (half frequency mode) pulse width (5) 4*t22 4*t22 4*t22 4*t22 4*t22 ns t34 sysclk (half frequency mode) clock high time (5) 2*t22-1 2*t22+1 2*t22-1 2*t22+1 ns t35 sysclk (half frequency mode) clock low time (5) 2*t22-1 2*t22+1 2*t22-1 2*t22+1 ns t36 aleset-up to sysclk falling 7 6 ns t37 alehold from sysclk falling 1 1 ns t38 a/dset-up to ale falling 8 8 ns t39 a/dhold from ale falling 1 1 ns t40 wr set-up to sysclk rising 8 7 ns t41 wr hold from sysclk rising 3 3 ns t42 clkin (1x clock mode) pulse width high (6) 13 11 (6) ns t43 clkin (1x clock mode) pulse width low (6) 13 11 (6) ns t44 clkin (1x clock mode) clock period (6) 30 50 25 50 ns tderate all outputs timing deration for loading 1 1 ns/ over c ld (3, 4) 25pf notes: 2889 tbl 11 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns .
5.5 16 idt79r3081 riscontroller military and commercial temperature ranges 20mhz 25mhz 33.33mhz 40mhz 50mhz symbol parameter test conditions min. max. min. max. min. max. min. max. min. max. units v oh output high voltage v cc = min., i oh = C4ma 3.5 3.5 3.5 3.5 3.5 v v ol output low voltage v cc = min., i ol = 4ma 0.4 0.4 0.4 0.4 0.4 v v ih input high voltage (3) 2.0 2.0 2.0 2.0 2.0 v v il input low voltage (1) 0.8 0.8 0.8 0.8 0.8 v v ihs input high voltage (2,3) 3.0 3.0 3.0 3.0 3.0 v v ils input low voltage (1,2) 0.4 0.4 0.4 0.4 0.4 v c in input capacitance (4) 10 10 10 10 10 pf c out output capacitance (4) 10 10 10 10 10 pf i cc operating current v cc = 5v, t a = 25 c 475 525 625 700 825 ma i ih input high leakage v ih = v cc 100 100 100 100 100 m a i il input low leakage v il = gnd C100 C100 C100 C100 C100 m a i oz output tri-state leakage v oh = 2.4v, v ol = 0.5v C100 100 C100 100 C100 100 C100 100 C100 100 m a dc electrical characteristics r3081 commercial temperature range ? (t c = 0 c to +85 c, v cc = +5.0v 5%) 2889 tbl 09 notes: 1. v il min. = C3.0v for pulse width less than 15ns. v il should not fall below -0.5v for larger periods. 2. v ihs and v ils apply to cikin and reset . 3. v ih should not be held above v cc + 0.5v. 4. guaranteed by design.
5.5 17 idt79r3081 riscontroller military and commercial temperature ranges 20mhz 25mhz symbol signals description min. max. min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 6 5 ns rdcen , cohreq t1a a/d set-up to sysclk falling 7 6 ns t2 busreq , ack , buserror , hold from sysclk rising 4 4 ns rdcen , cohreq t2a a/d hold from sysclk falling 2 2 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 10 10 ns burst / wrnear , rd , dataen t4 a/d, addr, diag, ale, wr driven from sysclk falling 10 10 ns burst / wrnear , rd , dataen t5 busgnt asserted from sysclk rising 8 7 ns t6 busgnt negated from sysclk falling 8 7 ns t7 wr , rd , burst / wrnear , a/d valid from sysclk rising 5 5 ns t8 ale asserted from sysclk rising 4 4 ns t9 ale negated from sysclk falling 4 4 ns t10 a/d hold from ale negated 2 2 ns t11 dataen asserted from sysclk falling 15 15 ns t12 dataen asserted from a/d tri-state (3) 00ns t14 a/d driven from sysclk rising (3) 00ns t15 wr , rd , dataen , burst / wrnear negated from sysclk falling 7 6 ns t16 addr(3:2) valid from sysclk 66ns t17 diag valid from sysclk 12 11 ns t18 a/d tri-state from sysclk falling 10 10 ns t19 a/d sysclk falling to data valid 13 12 ns t20 clkin (2x clock mode) pulse width high 10 8 ns t21 clkin (2x clock mode) pulse width low 10 8 ns t22 clkin (2x clock mode) clock period 25 250 20 250 ns t23 reset pulse width from v cc valid 200 200 m s t24 reset minimum pulse width 32 32 tsys t25 reset set-up to sysclk falling 6 5 ns t26 int mode set-up to reset rising 10 9 ns t27 int mode hold from reset rising 0 0 ns t28 sint , sbrcond set-up to sysclk falling 6 5 ns t29 sint , sbrcond hold from sysclk falling 3 3 ns t30 int , brcond set-up to sysclk falling 6 5 ns t31 int , brcond hold from sysclk falling 3 3 ns tsys sysclk (full frequency mode) pulse width (5) 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk (full frequency mode) clock high time (5) t22-2 t22+2 t22-2 t22+2 ns ac electrical characteristics r3081 commercial temperature range (1, 2) (20, 25mhz) (t c = 0 c to +85 c, v cc = +5.0v 5%) 2889 tbl 10 notes: 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40mhz and 50mhz. 7. when using the reduced frequency feature, the minimum allowed internal cpu speed is 0.5 mhz.
5.5 18 idt79r3081 riscontroller military and commercial temperature ranges 33mhz 40mhz symbol signals description min. max. min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 4 3 ns rdcen , cohreq t1a a/d set-up to sysclk falling 5 4.5 ns t2 busreq , ack , buserror , hold from sysclk rising 3 3 ns rdcen , cohreq t2a a/d hold from sysclk falling 1 1 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 10 10 ns burst / wrnear , rd , dataen t4 a/d, addr, diag, ale, wr driven from sysclk falling 10 10 ns burst / wrnear , rd , dataen t5 busgnt asserted from sysclk rising 6 5 ns t6 busgnt negated from sysclk falling 6 5 ns t7 wr , rd , burst / wrnear , a/d valid from sysclk rising 4 3.5 ns t8 ale asserted from sysclk rising 3 3 ns t9 ale negated from sysclk falling 3 3 ns t10 a/d hold from ale negated 1.5 1.5 ns t11 dataen asserted from sysclk falling 13 12 ns t12 dataen asserted from a/d tri-state (3) 0 0ns t14 a/d driven from sysclk rising (3) 0 0ns t15 wr , rd , dataen , burst / wrnear negated from sysclk falling 5 4 ns 20mhz 25mhz symbol signals description min. max. min. max. unit t33 sysclk (full frequency mode) clock low time (5) t22-2 t22+2 t22-2 t22+2 ns tsys/2 sysclk (half frequency mode) pulse width (5) 4*t22 4*t22 4*t22 4*t22 ns t34 sysclk (half frequency mode) clock high time (5) 2*t22-2 2*t22+2 2*t22-2 2*t22+2 ns t35 sysclk (half frequency mode) clock low time (5) 2*t22-2 2*t22+2 2*t22-2 2*t22+2 ns t36 ale set-up to sysclk falling 9 8 ns t37 ale hold from sysclk falling 2 2 ns t38 a/d set-up to ale falling 10 9 ns t39 a/d hold from ale falling 2 2 ns t40 wr set-up to sysclk rising 10 9 ns t41 wr hold from sysclk rising 3 3 ns t42 clkin (1x clock mode) pulse width high (6) 20 16 ns t43 clkin (1x clock mode) pulse width low (6) 20 16 ns t44 clkin (1x clock mode) clock period (6) 50 50 40 50 ns tderate all outputs timing deration for loading 1 1 ns/ over c ld (3, 4) 25pf ac electrical characteristics r3081 (cont.) commercial temperature range (1, 2) (20, 25mhz) ? (t c = 0 c to +85 c, v cc = +5.0v 5%) 2889 tbl 11 notes: 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40mhz and 50mhz. 7. when using the reduced frequency feature, the minimum allowed internal cpu speed is 0.5 mhz. ac electrical characteristics r3081 commercial temperature range (1, 2) (33, 40mhz) ? (t c = 0 c to +85 c, v cc = +5.0v 5%) 2889 tbl 11
5.5 19 idt79r3081 riscontroller military and commercial temperature ranges 33mhz 40mhz symbol signals description min. max. min. max. unit t16 addr(3:2) valid from sysclk 5 4.5 ns t17 diag valid from sysclk 10 9 ns t18 a/d tri-state from sysclk falling 9 8 ns t19 a/d sysclk falling to data valid 11 10 ns t20 clkin (2x clock mode) pulse width high 6.5 5.6 ns t21 clkin (2x clock mode) pulse width low 6.5 5.6 ns t22 clkin (2x clock mode) clock period 15 250 12.5 250 ns t23 reset pulse width from v cc valid 200 200 m s t24 reset minimum pulse width 32 32 tsys t25 reset set-up to sysclk falling 4 3 ns t26 int mode set-up to reset rising 8 7 ns t27 int mode hold from reset rising 0 0 ns t28 sint , sbrcond set-up to sysclk falling 4 3 ns t29 sint , sbrcond hold from sysclk falling 2 2 ns t30 int , brcond set-up to sysclk falling 4 3 ns t31 int , brcond hold from sysclk falling 2 2 ns tsys sysclk (full frequency mode) pulse width (5) 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk (full frequency mode) clock high time (5) t22-1 t22+1 t22-1 t22+1 ns t33 sysclk (full frequency mode) clock low time (5) t22-1 t22+1 t22-1 t22+1 ns tsys/2 sysclk (half frequency mode) pulse width (5) 4*t22 4*t22 4*t22 4*t22 ns t34 sysclk (half frequency mode) clock high time (5) 2*t22-1 2*t22+1 2*t22-1 2*t22+1 ns t35 sysclk (half frequency mode) clock low time (5) 2*t22-1 2*t22+1 2*t22-1 2*t22+1 ns t36 ale set-up to sysclk falling 7 6 ns t37 ale hold from sysclk falling 1 1 ns t38 a/d set-up to ale falling 8 8 ns t39 a/d hold from ale falling 1 1 ns t40 wr set-up to sysclk rising 8 7 ns t41 wr hold from sysclk rising 3 3 ns t42 clkin (1x clock mode) pulse width high (6) 13 11 (6) ns t43 clkin (1x clock mode) pulse width low (6) 13 11 (6) ns t44 clkin (1x clock mode) clock period (6) 30 50 25 50 ns tderate all outputs timing deration for loading over c ld (3, 4) 1 1 ns/ 25pf ac electrical characteristics r3081 (cont.) comercial temperature range (1, 2) (33, 40mhz) ? (t c = 0 c to +85 c, v cc = +5.0v 5%) 2889 tbl 11 notes: 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40 and 50mhz. 7. when using the reduced frequency feature, the minimum allowed internal cpu speed is 0.5 mhz.
5.5 20 idt79r3081 riscontroller military and commercial temperature ranges 50mhz symbol signals description min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 5 ns rdcen , cohreq t1a a/d set-up to sysclk falling 6 ns t2 busreq , ack , buserror , hold from sysclk rising 4 ns rdcen , cohreq t2a a/d hold from sysclk falling 2 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 10 ns burst / wrnear , rd , dataen t4 a/d, addr, diag, ale, wr driven from sysclk falling 10 ns burst / wrnear , rd , dataen t5 busgnt asserted from sysclk rising 7 ns t6 busgnt negated from sysclk falling 7 ns t7 wr , rd , burst / wrnear , a/d valid from sysclk rising 5 ns t8 ale asserted from sysclk rising 4 ns t9 ale negated from sysclk falling 4 ns t10 a/d hold from ale negated 1.5 ns t11 dataen asserted from sysclk falling 15 ns t12 dataen asserted from a/d tri-state (3) 0ns t14 a/d driven from sysclk rising (3) 0ns t15 wr , rd , dataen , burst / wrnear negated from sysclk falling 6 ns t16 addr(3:2) valid from sysclk 6ns t17 diag valid from sysclk 11ns t18 a/d tri-state from sysclk falling 10 ns t19 a/d sysclk falling to data valid 12 ns t20 clkin (2x clock mode) pulse width high n/a (8) ns t21 clkin (2x clock mode) pulse width low n/a (8) ns t22 clkin (2x clock mode) clock period n/a (7, 8) ns t23 reset pulse width from v cc valid 200 m s t24 reset minimum pulse width 32 tsys t25 reset set-up to sysclk falling 5 ns t26 int mode set-up to reset rising 9 ns t27 int mode hold from reset rising 0 ns t28 sint , sbrcond set-up to sysclk falling 5 ns t29 sint , sbrcond hold from sysclk falling 3 ns t30 int , brcond set-up to sysclk falling 5 ns t31 int , brcond hold from sysclk falling 3 ns tsys sysclk (full frequency mode) pulse width (5) n/a (8) n/a (8) ns t32 sysclk (full frequency mode) clock high time (5) n/a (8) n/a (8) ns t33 sysclk (full frequency mode) clock low time (5) n/a (8) n/a (8) ns ac electrical characteristics r3081 commercial temperature range (1, 2) (50mhz) ? (t c = 0 c to +85 c, v cc = +5.0v 5%) notes: 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40mhz and 50mhz. 7. when using the reduced frequency feature, the minimum allowed internal cpu speed is 0.5 mhz. 8. for the 50mhz version, 1x clock mode and half-frequency bus mode only. 2889 tbl 11
5.5 21 idt79r3081 riscontroller military and commercial temperature ranges ac electrical characteristics r3081 (cont.) comercial temperature range (1, 2) (50mhz) ? (t c = 0 c to +85 c, v cc = +5.0v 5%) 50mhz symbol signals description min. max. unit tsys/2 sysclk (half frequency mode) pulse width (5) 2*t44 2*t44 ns t34 sysclk (half frequency mode) clock high time (5) t44-1 t44+1 ns t35 sysclk (half frequency mode) clock low time (5) t44-1 t44+1 ns t36 ale set-up to sysclk falling 8 ns t37 ale hold from sysclk falling 2 ns t38 a/d set-up to ale falling 9 ns t39 a/d hold from ale falling 2 ns t40 wr set-up to sysclk rising 9 ns t41 wr hold from sysclk rising 3 ns t42 clkin (1x clock mode) pulse width high (6) 16 (6) ns t43 clkin (1x clock mode) pulse width low (6) 16 (6) ns t44 clkin (1x clock mode) clock period (6) 40 50 ns tderate all outputs timing deration for loading over c ld (3, 4) 1 ns/ 25pf notes: 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40mhz and 50mhz. 7. when using the reduced frequency feature, the minimum allowed internal cpu speed is 0.5 mhz. 8. for the 50mhz version, 1x clock mode and half-frequencybus mode only.
5.5 22 idt79r3081 riscontroller military and commercial temperature ranges ac electrical characteristics r3081 military temperature range (1, 2) ? (t c (7) = -55 c to +125 c, v cc = +5.0v 10%) 20mhz 25mhz symbol signals description min. max. min. max. unit t1 busreq , ack , buserror , set-up to sysclk rising 6 5 ns rdcen , cohreq t1a a/d set-up to sysclk falling 7 6 ns t2 busreq , ack , buserror , hold from sysclk rising 4 4 ns rdcen , cohreq t2a a/d hold from sysclk falling 2 2 ns t3 a/d, addr, diag, ale, wr tri-state from sysclk rising 10 10 ns burst / wrnear , rd , dataen t4 a/d, addr, diag, ale, wr driven from sysclk falling 10 10 ns burst / wrnear , rd , dataen t5 busgnt asserted from sysclk rising 8 7 ns t6 busgnt negated from sysclk falling 8 7 ns t7 wr , rd , burst / wrnear , a/d valid from sysclk rising 5 5 ns t8 ale asserted from sysclk rising 4.5 4.5 ns t9 ale negated from sysclk falling 4 4 ns t10 a/d hold from ale negated (3) 1.5 1.5 ns t11 dataen asserted from sysclk falling 15 15 ns t12 dataen asserted from a/d tri-state (3) 00ns t14 a/d driven from sysclk rising (3) 00ns t15 wr , rd , dataen , burst / wrnear negated from sysclk falling 7 6 ns t16 addr(3:2) valid from sysclk 66ns t17 diag valid from sysclk 12 11 ns 20mhz 25mhz symbol parameter test conditions min. max. min. max. units v oh output high voltage v cc = min., i oh = C4ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4ma 0.4 0.4 v v ih input high voltage (3) 2.0 2.0 v v il input low voltage (1) 0.8 0.8 v v ihs input high voltage (2,3) 2.8 2.8 v v ils input low voltage (1,2) 0.4 0.4 v c in input capacitance (4) 12 12 pf c out output capacitance (4) 12 12 pf i cc operating current v cc = 5.0v, t a = 25 c 550 650 ma i ih input high leakage v ih = vcc 100 100 m a i il input low leakage v il = gnd C100 C100 m a i oz output tri-state leakage v oh = 2.4v, v ol = 0.5v C100 100 C100 100 m a dc electrical characteristics r3081 military temperature range? (t c (5) = -55 c to +125 c, v cc = +5.0v 10%) 2889 tbl 09 notes: 1. v il min. = C3.0v for pulse width less than 15ns. v il should not fall below -0.5v for larger periods. 2. v ihs and v ils apply to cikin and reset . 3. v ih should not be held above v cc + 0.5v. 4. guaranteed by design. 5. case temperatures are "instant on."
5.5 23 idt79r3081 riscontroller military and commercial temperature ranges ac electrical characteristics r3081 (cont.) military temperature range (1, 2) ? (t c (7) = -55 c to +125 c, v cc = +5.0v 10%) 20mhz 25mhz symbol signals description min. max. min. max. unit t18 a/d tri-state from sysclk falling 10 10 ns t19 a/d sysclk falling to data valid 13 12 ns t20 clkin (2x clock mode) pulse width high 10 8 ns t21 clkin (2x clock mode) pulse width low 10 8 ns t22 clkin (2x clock mode) clock period 25 250 20 250 ns t23 reset pulse width from vcc valid 200 200 m s t24 reset minimum pulse width 32 32 tsys t25 reset set-up to sysclk falling 6 5 ns t26 int mode set-up to reset rising 10 9 ns t27 int mode hold from reset rising 0 0 ns t28 sint , sbrcond set-up to sysclk falling 6 5 ns t29 sint , sbrcond hold from sysclk falling 3.5 3 ns t30 int , brcond set-up to sysclk falling 6 5 ns t31 int , brcond hold from sysclk falling 3.5 3 ns tsys sysclk (full frequency mode) pulse width (5) 2*t22 2*t22 2*t22 2*t22 ns t32 sysclk (full frequency mode) clock high time (5) t22-2 t22+2 t22-2 t22+2 ns t33 sysclk (full frequency mode) clock low time (5) t22-2 t22+2 t22-2 t22+2 ns tsys/2 sysclk (half frequency mode) pulse width (5) 4*t22 4*t22 4*t22 4*t22 ns t34 sysclk (half frequency mode) clock high time (5) 2*t22-2 2*t22+2 2*t22-2 2*t22+2 ns t35 sysclk (half frequency mode) clock low time (5) 2*t22-2 2*t22+2 2*t22-2 2*t22+2 ns t36 ale set-up to sysclk falling 9 8 ns t37 ale hold from sysclk falling 2 2 ns t38 a/d set-up to ale falling 10 9 ns t39 a/d hold from ale falling 2 2 ns t40 wr set-up to sysclk rising 10 9 ns t41 wr hold from sysclk rising 3 3 ns t42 clkin (1x clock mode) pulse width high (6) 20 16 ns t43 clkin (1x clock mode) pulse width low (6) 20 16 ns t44 clkin (1x clock mode) clock period (6) 50 50 40 50 ns tderate all outputs timing deration for loading 1 1 ns/ over c ld (3, 4) 25pf notes: 2889 tbl 11 1. all timings referenced to 1.5v. all timings measured with respect to a 2.5ns rise and fall time. 2. the ac values listed here reference timing diagrams contained in the r3081 family hardware user's manual . 3. guaranteed by design. 4. this parameter is used to derate the ac timings according to the loading of the system. this parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pf over the specified test load condition. 5. in 1x clock mode, t22 is replaced by t44/2. 6. in 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns. 7. case temperatures are "instant on."
5.5 24 idt79r3081 riscontroller military and commercial temperature ranges pin configurations note: reserved pins must not be connected. vss vcc a/d(14) a/d(13) a/d(12) a/d(11) a/d(10) a/d(9) vcc vss a/d(8) a/d(7) a/d(6) a/d(5) a/d(4) a/d(3) vss vcc a/d(2) a/d(1) a/d(0) burst/wrnear addr(3) addr(2) vcc vss diag(1) ale rd wr dataen vcc vss sysclk busgnt reset buserror ack rdcen busreq brcond(0) vss vcc clkin rsvd(4) rsvd(3) rsvd(2) rsvd(1) cohreq int(5) vss vcc int(4) int(3) sint(2) sint(1) sint(0) sbrcond(3) sbrcond(2) nc vss vcc a/d(15) a/d(16) a/d(17) a/d(18) a/d(19) a/d(20) vss vcc a/d(21) a/d(22) a/d(23) a/d(24) a/d(25) a/d(26) vcc vss a/d(27) a/d(28) a/d(29) a/d(30) a/d(31) 184 12 75 33 54 diag(0)/ ivdreq 2889 drw 08 84-pin mquad/plcc top view
5.5 25 idt79r3081 riscontroller military and commercial temperature ranges vss vcc a/d(14) a/d(13) a/d(12) a/d(11) a/d(10) a/d(9) vcc vss a/d(8) a/d(7) a/d(6) a/d(5) a/d(4) a/d(3) vss vcc a/d(2) a/d(1) a/d(0) burst/wrnear addr(3) addr(2) vcc vss diag(1) ale rd wr dataen vcc vss sysclk busgnt reset buserror ack rdcen busreq brcond(0) vss vcc clkin rsvd(4) rsvd(3) rsvd(2) rsvd(1) cohreq int(5) vss vcc int(4) int(3) sint(2) sint(1) sint(0) sbrcond(3) sbrcond(2) nc vss vcc a/d(15) a/d(16) a/d(17) a/d(18) a/d(19) a/d(20) vss vcc a/d(21) a/d(22) a/d(23) a/d(24) a/d(25) a/d(26) vcc vss a/d(27) a/d(28) a/d(29) a/d(30) a/d(31) 1 84 21 75 43 64 diag(0)/ ivdreq 63 42 22 pin configurations note: reserved pins must not be connected. 84-pin fd top view
5.5 26 idt79r3081 riscontroller military and commercial temperature ranges 2905 drw 06 1 12 13 14 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 54 52 53 55 56 57 58 59 60 51 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 rv3081 y 100-pin tqfp (cavity up) top view v cc a/d(14) a/d(13) a/d(12) a/d(11) a/d(10) a/d(9) v cc v ss a/d(8) a/d(7) a/d(6) a/d(5) a/d(4) a/d(3) v ss v cc a/d(2) a/d(1) a/d(0) nc nc nc nc v ss sbrcond(2) sbrcond(3) v cc clkin int(5) v ss v cc int(4) int(3) sint(2) sint(1) sint(0) v ss v cc nc nc nc rsvd(4) rsvd(3) rsvd(2) rsvd(1) cohreq v ss v ss v cc burst/wrnear addr(3) addr(2) diag(1) ale rd wr dataen v cc v ss sysclk busgnt reset buserror ack rdcen busreq v cc v ss brcond(0) diag0/ ivdreq v ss v cc v ss v cc a/d(15) a/d(16) a/d(17) a/d(18) a/d(19) a/d(20) a/d(21) a/d(22) a/d(23) a/d(24) a/d(25) a/d(26) a/d(27) a/d(28) a/d(29) a/d(30) a/d(31) v cc v ss v cc v ss nc v ss v ss v cc
5.5 27 idt79r3081 riscontroller military and commercial temperature ranges figure 8 (a). r3081 clocking (1x clock input mode, full frequency bus) figure 8 (b). r3081clocking (1x clock input mode, half-frequency bus) figure 8 (c). r3081 clocking (2x clock input mode, half-frequency bus) figure 8 (d). r3081 clocking (2x clock input mode, full-frequency bus) clkin sysclk t 42 t 43 t 44 t 32 t sys t 33 2889 drw 12 clkin sysclk t 42 t 43 t 44 t 34 t sys/2 t 35 2889 drw 13 clkin sysclk t 20 t 21 t 22 t 35 t sys/2 t 34 2889 drw 14 clkin sysclk t 20 t 21 t 22 t 32 t sys t 33 2889 drw 15
5.5 28 idt79r3081 riscontroller military and commercial temperature ranges figure 9. power-on reset sequence figure 10. warm reset sequence figure 11. mode selection and negation of reset vcc clkin reset t 23 2889 drw 16 clkin reset t 24 2889 drw 17 sysclk reset int(n) t 25 t 26 t 27 2889 drw 18
5.5 29 idt79r3081 riscontroller military and commercial temperature ranges figure 12. single datum read in r3081 sysclk rd a/d(31:0) ale addr(3:2) dataen rdcen ack burst diag(1) diag(0) addr be word address start read turn bus ack? ack? sample data end read ack/ rdcen cached? i/d miss address(2) miss address(3) data input t 7 t 14 t 10 t 8 t 9 t 7 t 12 t 1 t 2 t 15 t 2a t 15 t 1a t 14 t 17 t 17 t 18 t 16 t 11 2889 drw 19
5.5 30 idt79r3081 riscontroller military and commercial temperature ranges figure 13. r3081 burst read sysclk rd a/d(31:0) ale addr(3:2) dataen rdcen ack burst diag(1) diag(0) addr be '00' start read turn bus sample data new transaction ack/ rdcen cached? i/d t 7 t 14 t 10 t 8 t 9 t 7 t 12 t 1 t 2 t 17 t 17 t 18 t 15 word 0 t 2a t 1a t 14 t 15 word 1 t 2a t 1a word 2 t 2a t 1a word 3 t 2a t 1a '01' '10' '11' t 1 t 2 t 1 t 2 t 1 t 2 t 16 t 16 t 16 sample data sample data sample data rdcen rdcen rdcen miss address(2) miss address(3) t 16 t 11 2889 drw 20
5.5 31 idt79r3081 riscontroller military and commercial temperature ranges figure 14 (b). end of throttled quad read figure 14 (a). start of throttled quad read sysclk rd a/d(31:0) ale addr(3:2) dataen rdcen ack burst '00' sample data t 1 t 2 word 0 t 2a t 1a word 1 t 2a t 1a '01' '10' t 1 t 2 t 1 t 2 t 16 t 16 sample data sample data rdcen rdcen rdcen 2889 drw 21 sysclk rd a/d(31:0) ale addr(3:2) dataen rdcen ack burst new transaction ack t 15 t 14 t 15 t 2a t 1a word 2 word 3 t 2a t 1a '01' '11' t 1 t 2 t 1 t 2 t 1 t 2 t 16 sample data sample data rdcen rdcen t 1 t 2 2889 drw 22
5.5 32 idt79r3081 riscontroller military and commercial temperature ranges figure 16. request and relinquish of r3081 bus to external master figure 15. r3081 write cycle sysclk wr a/d(31:0) ale addr(3:2) ack wrnear diag(1) diag(0) addr be word address start write data out ack? ack? negate wr new transfer ack t 7 t 14 t 10 t 8 t 9 t 7 t 1 t 2 t 15 t 14 t 19 data out t 15 t 16 t 17 t 17 reserved reserved reserved cached 2889 drw 23 a/d(31:0) addr(3:2) diag(1:0) sysclk busreq busgnt rd wr ale burst/ wrnear t 1 t 2 t 5 t 3 2889 drw 24
5.5 33 idt79r3081 riscontroller military and commercial temperature ranges figure 17. r3081 regaining bus mastership sysclk busreq busgnt a/d(31:0) addr(3:2) diag(1:0) rd wr ale burst/ wrnear t 1 t 2 t 6 t 4 2889 drw 25 figure 18. synchronized interrupt input timing figure 19. direct interrupt input timing sysclk int(n) t 30 t 31 2889 drw 27 sysclk sint(n) t 28 t 29 2889 drw 26
5.5 34 idt79r3081 riscontroller military and commercial temperature ranges figure 20. synchronized branch condition input timing sysclk sbrcond(n) t 28 t 29 2889 drw 28 figure 22. coherent dma request sysclk busreq busgnt a/d(31:0) addr(3:2) diag(1:0) rd wr ale burst/ wrnear cohreq t 1 t 2 t 5 t 3 2889 drw 30 figure 21. direct branch condition input timing sysclk brcond(n) t 30 t 31 2889 drw 29
5.5 35 idt79r3081 riscontroller military and commercial temperature ranges figure 23. beginning of coherent dma write sysclk wr ale a/d addr internal invalidate address t 36 t 37 t 40 t 41 t 38 t 39 2889 drw 31 figure 24. cache word invalidation sysclk ack ivdreq internal ivd internal invalidate address t 1 t 2 2988 drw 32 figure 25. end of coherent write sysclk ack wr t 40 t 41 2889 drw 33
5.5 36 idt79r3081 riscontroller military and commercial temperature ranges figure 26. end of coherent dma request sysclk busreq busgnt a/d(31:0) addr(3:2) diag(1:0) rd wr ale burst/ wrnear cohreq t 1 t 2 t 6 t 4 2889 drw 34
5.5 37 idt79r3081 riscontroller military and commercial temperature ranges notes: 1. all dimensions are in inches, unless otherwise noted. 2. bscbasic lead spacing between centers. 3. d & e do not include mold flash or protutions. 4. formed leads shall be planar with respect to one another and within .004 inches at the seating plane. 5. nd & ne represent the number of leads in the d & e directions respectively. 6. d1 & e1 should be measured from the bottom of the package. 7. mquad is pin & form compatible with plcc. 2874 drw 27 d d1 pin 1 e1 e e 45 x .045 b c1 seating plane d2/e2 d3/e3 b1 c a a1 84 lead plcc/mquad (7) (square) dwg # j84-1 mj84-1 # of leads 84 84 symbol min. max. min. max. a 165 .180 165 .180 a1 .095 .115 .094 .114 b .026 .032 .026 .032 b1 .013 .021 .013 .021 c .020 .040 .020 .040 c1 .008 .012 .008 .012 d 1.185 1.195 1.185 1.195 d1 1.150 1.156 1.140 1.150 d2/e2 1.090 1.130 1.090 1.130 d3/e3 1.000 ref 1.000 ref e 1.185 1.195 1.185 1.195 e1 1.150 1.156 1.140 1.150 e .050 bsc .050 bsc nd/ne 21 21
5.5 38 idt79r3081 riscontroller military and commercial temperature ranges ordering information idt xxxxx device type xx speed x package Cx process/ temp. range blank b m mj fd j pf 20 25 33 40 50 79r3081 79r3081e 79rv3081 79rv3081e commercial temperature range compliant to mil-std-883, class b military temperature range only 84-pin mquad 84-lead cavity-down flatpack with integral thermal slug 84-lead plcc 100-lead tqfp 20.0mhz 25.0mhz 33.33mhz 40.0mhz 50.0mhz no tlb; v cc = 5v with tlb; v cc = 5v no tlb; v cc = 3.3v with tlb; v cc = 3.3v 2889 drw 37 5v only valid combinations idt 79r3081 (e) C 20, 25, 33, 40, 50 mj package 79rv3081 (e) C 20, 25, 33 pf package 79rv3081(e) C 20, 25, 33, 40 mj package 79r3081e C 20, 25 (fdb/fdm) fd package only (5v only)

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